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A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 64mb synchronous dram specification A2V64S40CTP zentel electronics corp . 6f-1, no. 1-1, r&d rd. ii, hsin chu science park, 300 taiwan, r.o.c. tel:886-3-579-9599 fax:886-3-579-9299 www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 1/36 general description the A2V64S40CTP is 67,108,864 bits synchronous high data ra te dynamic ram organized as 4 x 1,048,576 words by 16 bits. synchronous desi gn allows precise cy cle controls with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programm able burst length and programmabl e latencies allow the same device to be useful for a variety of high bandwidt h, high performance memory system applications. features ? 3.3v power supply ? all inputs are sampled at the positive going ? lvttl compatible with multiplexed a ddress edge of the system clock ? four banks operation ? auto & self refresh ? mrs cycle with address key programs ? 64ms refresh period (4k cycle) - cas latency (2 & 3) ? burst read single write operation - burst length (1, 2, 4, 8 & full page) ? ldqm & udqm for masking - burst type (sequential & interleave) pin configurations ordering information 54pin tsopii (400mil x 875mil) part no. max. frequency supply voltage A2V64S40CTP-g5 200mhz (cl=3) 3.3v A2V64S40CTP-g6 166mhz (cl=3) 3.3v A2V64S40CTP-g7 143mhz (cl=3) 3.3v zentel electronics reserves the right to change products or specification without notice. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 2/36 block diagram note:this figure shows the a2v64s30ctp the a2v64s20ctp configuration is 4096x1024x4 of cell array and dq0-3 the A2V64S40CTP configuration is 4069x256x16 of cell array and dq0-15 type designation code a ??g speed grade 7 143mhz@cl=3 6 166mhz@cl=3 5 200mhz@cl=3 package type tp tsop (ii) process generation function reserved for future use organization 2 n 3 x8, 4 x16 sdr synchronous dram density 64 64m bits interface v lvttl memory style (dram) zentel dram www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 3/36 pin descriptions symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. cke input clock enable: cke activates (high) and deactivat es (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank ), deep power down (all banks idle), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh m odes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. /cs input chip select: /cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when /cs is registered high. /cs provides for external bank selection on systems with multiple banks. /cs is considered part of the command code. /cas, /ras, /we input command inputs: /cas, /ras, and /we (along with /cs) define the command being entered. ldqm, udqm, input input/output mask: dqm is sample d high and is an input mask si gnal for write accesses and an output enable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when during a read cycle. ldqm corresponds to dq0?dq7, udqm corresponds to dq8?dq15. ldqm and udqm are considered same state when referenced as dqm. ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pi ns also select between the mode register and the extended mode register. a0?a11 input address inputs: a0?a11 are sampled during the active command (row address a0?a11) and read/write command (column-address a0?a7; with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address i nputs also provide the op-code during a load mode register command. dq0?dq15 i/o data input/output: data bus. nc ? internally not connected: these could be left unconnected, but it is recommended they be connected or v ss . v dd q supply dq power: provide isolated power to dqs for improved noise immunity. v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. v dd supply core power supply. v ss supply ground. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 4/36 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in ,v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma notes: permanent device damage may occur if abs olute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) parameter symbol min typ max unit note v dd 3.0 3.3 3.6 v supply voltage v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 v ddq + 0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -0.1ma output logic low voltage v ol - - 0.4 v i ol = 0.1ma input leakage current i li -5 - 5 ua 3 output leakage current i ol -5 - 5 ua 3 note: 1. vih(max) = 4.6v ac for pulse width 10ns acceptable. 2. vil(min) = -1.5v ac for pulse width 10ns acceptable. 3. any input 0v vin vdd + 0.3v, all other pins are not under test = 0v. 4. dout is disabled , 0v vout vdd. capacitance ( vdd =3.3v, t a = 25c , f = 1mhz ? parameter symbol min max unit note clock cclk 2.0 4.0 pf /cas,/ras,/we,/cs,cke,l/udqm cin 2.0 4.0 pf address c add 2.0 4.0 pf dq0~dq15 c out 3.0 6.0 pf www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 5/36 dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = 0 to 70 c) version parameter symbol test condition -5 -6 -7 unit note operating current (one bank active) i cc1 burst length = 1 t rc R t rc (min) i o = 0 ma 80 70 60 ma 1 i cc2 p cke Q v il (max), t cc = 10ns 2 2 2 precharge standby current in power-down mode i cc2 ps cke & clk Q v il (max), t cc = 1 1 1 ma i cc2 n cke R v ih (min), cs R v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 20 20 precharge standby current in non power-down mode i cc2 ns cke R v ih (min), clk Q v il (max), t cc = input signals are stable 15 15 15 ma i cc3 p cke Q v il (max), t cc = 10ns 10 10 10 active standby current in power-down mode i cc3 ps cke & clk Q v il (max), t cc = 10 10 10 ma i cc3 n cke R v ih (min), cs R v ih (min), t cc = 10ns input signals are changed one time during 20ns 30 25 20 active standby current in non power-down mode (one bank active) i cc3 ns cke R v ih (min), clk Q v il (max), t cc = input signals are stable 10 10 10 ma operating current (burst mode) i cc 4 i o = 0 ma page burst 4banks activated t ccd = 2clks 100 90 80 ma 1 refresh current i cc 5 t arfc R t arfc (min) 150 130 110 ma 2 self refresh current i cc 6 cke Q 0.2v 1.5 1.5 1.5 ma notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. unless otherwise noted, input swing ievei is cmos(vih /vil=vddq/vssq). www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 6/36 ac operating test conditions (v dd = 3.3v, t a = 0 to 70 c) parameter value unit ac input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see figure 2 www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 7/36 operating ac parameter (ac operating conditions unless otherwise noted) version parameter symbol -5 -6 -7 unit note row active to row active delay t rrd (min) 10 12 14 ns 1 ras to cas delay t rcd (min) 15 18 21 ns 1 row precharge time t rp (min) 15 18 21 ns 1 t ras (min) 40 40 42 ns 1 row active time t ras (max) 100 100 100 us row cycle time t rc (min) 50 58 63 ns 1 last data in to row precharge t rdl (min) 2 2 2 clk 2 last data in to active delay t dal (min) 6 5 5 clk- last data in to new col. address delay t cdl (min) 1 1 1 clk 2 last data in to burst stop t bdl (min) 1 1 1 clk 2 auto refresh cycle time t arfc (min) 50 60 70 ns notes: 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then roundi ng off to the next higher integer. 2. minimum delay is required to complete write. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 8/36 ac characteristics (ac operating conditions unless otherwise noted) -5 -6 -7 parameter symbol min max min max min max unit note cas latency=3 t cc (3) 5 6 7 clk cycle time cas latency=2 t cc (2) 10 10 10 ns 1 cas latency=3 t sac (3) 4.5 4.5 4.5 clk to valid output delay cas latency=2 t sac (2) 4.5 4.5 ns 1,2 cas latency=3 t oh (3) 2 2 2 output data hold time cas latency=2 t oh (2) 2 2 ns 2 clk high pulse width t ch 2 2.5 2.5 ns 3 clk low pulse width t cl 2 2.5 2.5 ns 3 input setup time t ss 1.5 1.5 ns 3 input hold time t sh 1 1 ns 3 clk to output in low-z t slz 1 1 ns 2 cas latency=3 4.5 4.5 4.5 clk to output in hi-z cas latency=2 t shz 4.5 4.5 ns notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 9/36 truth table command truth table command symbol cken-1 cken /cs /ras /cas /we ba1 ba0 a10/ ap a11, a9 ~ a0 device deselect dsl h x h x x x x x x x no operation nop h x l h h h x x x x burst stop bst h x l h h l x x x x read rd h x l h l h v v l v read with auto precharge rda h x l h l h v v h v write wr h x l h l l v v l v write with auto precharge wra h x l h l l v v h v bank activate act h x l l h h v v v v precharge select bank pre h x l l h l v v l x precharge all banks pall h x l l h l x x h x mode register set mrs h x l l l l l l l x extended mode register set emrs h x l l l l h l l v (v=valid, x=don t care, h=logic high, l=logic low) cke truth table current state function symbol cken-1 cken /cs /ras /cas /we /address activating clock suspend mode entry h l x x x x x any clock suspend mode l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle auto refresh command ref h h l l l h x idle self refresh entry sref h l l l l h x idle power down entry pd h l l h h h x h l h x x x x idle deep power down entry dpd h l l h h l x self refresh self refresh exit l h l h h h x l h h x x x x power down power down exit l h l h h h x l h h x x x x deep power down deep power down exit l h x x x x x (v=valid, x=don t care, h=logic high, l=logic low) www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 10/36 function truth table current state /cs /ras /cas /we /address command action notes h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 rd/rda illegal 1 l h l l ba,ca,a10 wr/wra illegal 1 l l h h ba,ra act row activating l l h l ba,a10 pre/pall nop l l l h x ref auto refresh l l l l oc,ba1=l mrs mode register set idle l l l l oc,ba1=h emrs extended mode register set h x x x x desl nop l h h h x nop nop l h h l x bst nop l h l h ba,ca,a10 rd/rda begin read 2 l h l l ba,ca,a10 wr/wra begin write 2 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall precharge / precharge all banks 3 l l l h x ref illegal row active l l l l oc,ba mrs / emrs illegal h x x x x desl continue burst to end row active l h h h x nop continue burst to end row active l h h l x bst burst stop row active l h l h ba,ca,a10 rd/rda terminate burst,begin new read 4 l h l l ba,ca,a10 wr/wra terminate burst,begin write 4,5 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall terminate burst precharging l l l h x ref illegal read l l l l oc,ba1=l mrs / emrs illegal h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst burst stop row active l h l h ba,ca,a10 rd/rda terminate burst, start read : determine ap 4,5 l h l l ba,ca,a10 wr/wra terminate burst,new write : determine ap 4 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall terminate burst precharging 6 l l l h x ref illegal write l l l l oc,ba1=l mrs / emrs illegal h x x x x desl continue burst to end precharging l h h h x nop continue burst to end precharging l h h l x bst illegal l h l h ba,ca,a10 rd/rda illegal 1 l h l l ba,ca,a10 wr/wra illegal 1 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall illegal 1 l l l h x ref illegal read with auto precharge l l l l oc,ba1=l mrs / emrs illegal h x x x x desl continue burst to end write recovering l h h h x nop continue burst to end write recovering l h h l x bst illegal l h l h ba,ca,a10 rd/rda illegal 1 l h l l ba,ca,a10 wr/wra illegal 1 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall illegal 1 l l l h x ref illegal write with auto precharge l l l l oc,ba1=l mrs / emrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 11/36 current state /cs /ras /cas /we /address command action notes h x x x x desl nop enter idle after trp l h h h x nop nop enter idle after trp l h h l x bst illegal l h l h ba,ca,a10 rd/rda illegal 1 l h l l ba,ca,a10 wr/wra illegal 1 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall nop enter idle after trp l l l h x ref illegal precharging l l l l oc,ba mrs/emrs illegal h x x x x desl nop enter bank active after trcd l h h h x nop nop enter bank active after trcd l h h l x bst illegal l h l h ba,ca,a10 rd/rda illegal 1 l h l l ba,ca,a10 wr/wra illegal 1 l l h h ba,ra act illegal 1,7 l l h l ba,a10 pre/pall illegal 1 l l l h x ref illegal row activating l l l l oc,ba mrs / emrs illegal h x x x x desl nop enter row active after tdpl l h h h x nop nop enter row active after tdpl l h h l x bst nop enter row active after tdpl l h l h ba,ca,a10 rd/rda begin read 5 l h l l ba,ca,a10 wr/wra begin new write l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall illegal 1 l l l h x ref illegal write recovering l l l l oc,ba1=l mrs / emrs illegal h x x x x desl nop enter precharge after tdpl l h h h x nop nop enter precharge after tdpl l h h l x bst nop enter precharge after tdpl l h l h ba,ca,a10 rd/rda illegal l h l l ba,ca,a10 wr/wra illegal 1,5 l l h h ba,ra act illegal 1 l l h l ba,a10 pre/pall illegal 1 l l l h x ref illegal write recovering with auto precharge l l l l oc,ba1=l mrs / emrs illegal h x x x x desl nop enter idle after trc1 l h h h x nop nop enter idle after trc1 l h h l x bst nop enter idle after trc1 l h l h ba,ca,a10 rd/rda illegal l h l l ba,ca,a10 wr/wra illegal l l h h ba,ra act illegal l l h l ba,a10 pre/pall illegal l l l h x ref illegal refresh l l l l oc,ba1=l mrs / emrs illegal h x x x x desl nop enter idle after trsc l h h h x nop nop enter idle after trsc l h h l x bst nop enter idle after trsc l h l h ba,ca,a10 rd/rda illegal l h l l ba,ca,a10 wr/wra illegal l l h h ba,ra act illegal l l h l ba,a10 pre/pall illegal l l l h x ref illegal mode register accessing l l l l mode mrs illegal www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 12/36 notes: 1. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 2. illegal if trcd is not satisfied. 3. illegal if tras is not satisfied. 4. must satisfy burst interrupt condition. 5. must satisfy bus contention, bus turn around, and/or write recovery requirements. 6. must mask preceding data which don't satisfy tdpl. 7. illegal if trrd is not satisfied www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 13/36 a. mode register field table to program modes register programmed with normal mrs address ba0 ~ ba1 a11 ~ a10/ap a9 *2 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu *1 w.b.l test mode cas latency bt burst length normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 0 0 setting for normal mrs 1 1 1 full page reserved b. power up sequence 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. c. burst sequence order of accesses within a burst burst length starting column address type=sequential type=interleaved a0 0 0-1 0-1 2 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 4 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 8 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n=a0 ? a8 (location 0 ? y) cn, cn+1, cn+2, cn+3, cn+4..., ?cn-1, cn? not supported note: 1. for full-page accesses: y = 512. 2. for a burst length of two, a1?a8 select the block-of-t wo burst; a0 selects the starting column within the block. 3. for a burst length of four, a2?a8 select the block-of-four burst; a0?a1 select the starting column within the block. 4. for a burst length of eight, a3?a8 select the block-of-ei ght burst; a0?a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0?a8 select the starting column. 6. whenever a boundary of the block is reached within a giv en sequence above, the following access wraps within the block. 7. for a burst length of one, a0?a8 select the unique colu mn to be accessed, and mode register bit m3 is ignored. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 14/36 power-up sequence power-up sequence the sdram should be goes on the following sequence with power up. the clk, cke, /cs, dqm and dq pi ns keep low till power stabilizes. the clk pin is stabilized within 100 s after power st abilizes before the following initialization sequence. the cke and dqm is driven to high between powe r stabilizes and the initialization sequence. this sdram has vdd clamp diodes for clk, cke, address, /ras, /cas, /we, /cs, dqm and dq pins. if the sepins go high before power up, the large current flows from these pins to vdd through the diodes. initialization sequence when 200 s or more has past after the above power-up sequence, all banks must be prec harged using the precharge command (pall). after trp delay, set 8 or more auto refres h commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by ke eping dqm and cke to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contentio n on memory system formed with a number of device. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 15/36 operation of the sdram read/write operations bank active before executing a read or write operation, the correspondi ng bank and the row address must be activated by the bank active (act) command. an interval of trcd is required between the bank active command input and the following read/write command input. read operation a read operation starts when a read comma nd is input. output buffer becomes low-z in the (/cas latency - 1) cycle after read command set. the sdram can perform a burst read operation. the burst length can be set to 1, 2, 4 and 8. the start address for a burst read is specified by the column address and the bank select address at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the /cas latency. the /cas latency can be set to 2 or 3. when the burst length is 1, 2, 4 and 8 the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the /cas latency and burst length must be specified at the mode register. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 16/36 write operation burst write or single write mode is selected 1. burst write: a burst write oper ation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4 and 8, like burst read operations. the write start address is s pecified by the column address and the ba nk select address at the write command set cycle. . 2. single write: a single write operation is enabled by setting op code (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select addre ss specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 17/36 auto precharge read with auto-precharge in this operation, since precharge is automatically performed after comp leting a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (act) command. in addition, an interval defined by l apr is required before executio n of the next command. [clock cycle time] /cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output write with auto-precharge in this operation, since precharge is automatically performed after completing a bu rst write or single write operation, a precharge command need not be executed after each write operat ion. the command executed for the same bank after the execution of this command must be the bank acti ve (act) command. in add ition, an interval of l dal is required between the final valid data input and input of next command. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 18/36 burst stop command during a read cycle, when the burst stop command is issued, the burst read data are termi nated and the data bus goes to high-z after the /cas latency from the burst stop command. during a write cycle, when the burst st op command is issued, the burst write data are terminated and data bus goes to high-z at the same clock with the burst stop command. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 19/36 command intervals read command to read command interval 1. same bank, same row address: when another read comm and is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 20/36 write command to write command interval 1. same bank, same row address: when another write command is ex ecuted at the same row address of the same bank as the preceding write command, the second write can be performed after an interv al of no less than 1 clock. in the case of burst writes, the second write command has priority. 2. same bank, different row address: when the row address changes, consecutiv e write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the ba nk active state. in the case of burst write, the second write command has priority. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 21/36 read command to write command interval 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be perform ed after an interval of no less than 1 clock. however, udqm and ldqm must be set high so that the out put buffer becomes high-z before data input. 2. same bank, different row address: when the row address changes, consecutiv e write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. different bank: when the bank change s, the write command can be performed afte r an interval of no less than 1 cycle, provided that the other bank is in the bank active state. however, udqm and ld qm must be set high so that the output buffer becomes high-z before data input. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 22/36 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be wr itten until one clock before the read command is executed. 2. same bank, different row address: when the row address changes, consecutiv e read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the ba nk active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 23/36 read with auto precharge to read command interval 1. different bank: when some banks are in the active stat e, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next cl ock of the second command. 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (anothe r bank) is executed. in the case of burst writes, the second write command has priority. t he internal auto-precharge of one bank starts 2 clocks later from the second command. 2. same bank: the consecutive writ e command (the same bank) is illegal. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 24/36 read with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write comm and (another bank) is executed. however, udqm and ldqm must be set high so that the output bu ffer becomes high-z before data input. the internal auto-precharge of one bank starts at the next clock of the second command. 2. same bank: the consecutive write command from read with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. write with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. however, in case of a burst write, data will continue to be written until one clock before t he read command is executed. the internal auto-precharge of one bank starts at 2 clocks later from the second command. 2. same bank: the consecutive read command from write with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 25/36 read command to precharge command interval (same bank) when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the out put buffer then becomes high-z after the clocks defined by l hzp, there is a case of interruption to burst read data out put will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by l ep must be assured as an interval from the final data output to precharge command execution. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 26/36 write command to precharge command interval (same bank) when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. howeve r, if the burst write oper ation is unfinished, the i nput data must be masked by means of udqm and ldqm for assurance of the clock defined by tdpl. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 27/36 bank active command interval 1. same bank: the interval between the two bank active commands must be no less than trc. 2. in the case of different bank active commands: the interv al between the two bank active commands must be no less than trrd. mode register set to bank active command interval the interval between setting the mode register and executing a bank active command must be no less than l mrd. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 28/36 dqm control the udqm and ldqm mask the upper and lower bytes of the dq data, respectively. the timing of udqm and ldqm is different during reading and writing. reading when data is read, the output buffer can be controlled by udqm and ldqm. by setting udqm and ldqm to low, the output buffer becomes low-z, enabling data output. by setting udqm and ldqm to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal re ading operations continue. the latency of udqm and ldqm during reading is 2 clocks. writing input data can be masked by udqm and ldqm. by setting dqm to low, data can be written. in addition, when udqm and ldqm are set to high, the corresponding data is not written, and the previous data is held. t he latency of udqm and ldqm during writing is 0 clock. www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 29/36 refresh auto-refresh all the banks must be precharged before executing an auto-r efresh command. since the auto-refresh command updates the internal counter every time it is executed and determine s the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycles are required to refresh al l the row addresses within tref (max.). the output buffer becomes high-z after auto-refresh start. in add ition, since a precharge has been completed by an internal operation after the auto-refresh, an additional prechar ge operation by the precharge command is not required. self-refresh after executing a self-refresh command, t he self-refresh operation continues while cke is held low. during selfrefresh operation, all row addresses are refreshed by the internal refr esh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refr esh addresses in or within tref (max.) period on the condition 1 and 2 below. 1. enter self-refresh mode within time as below* after either bur st refresh or distributed refresh at equal interval to all ref resh addresses are completed. 2. start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting fro m self-refresh mode. note: tref (max.) / refresh cycles. others power-down mode the sdram enters power-down mode when cke goes low in the id le state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram exits from the power down mode, and comm and input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode by driving cke to low during a bank active or read/write operation, the sdram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the in ternal state is maintained. when cke is driven high, the sdram terminates clock suspend mode, and command input is ena bled from the next clock. for details, refer to the "cke truth table". www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 30/36 timing waveforms read cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 31/36 write cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 32/36 mode register set cycle read cycle/write cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 33/36 read/single write cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 34/36 read/burst write cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 35/36 auto refresh cycle self refresh cycle www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 36/36 clock suspend mode www.datasheet.co.kr datasheet pdf - http://www..net/
A2V64S40CTP 64m single data rate synchronous dram revision 2.1 sep., 2008 page 37/36 power down mode initialization sequence www.datasheet.co.kr datasheet pdf - http://www..net/

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